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## Methods for the Application of Programmable Logic Devices in Electronic Protection Systems for High Energy Particle Accelerators

### Maciej Kwiatkowski

#### Abstract

The present thesis was realised within the framework of the Doctoral Student programme at the European Organisation for Nuclear Research CERN, which is situated near Geneva. The aim of this thesis was to develop a method for reliable firmware implementation and to use that method to implement a new firmware for the Safe Machine Parameters (SMP) system. That system relies heavily on the Field Programmable Gate Arrays (FPGA) and it is one of the key machine protection systems of the Large Hadron Collider (LHC). The conception of the SMP hardware originates from the fully tested Beam Interlock System (BIS) being a result of another PhD thesis. For that reason the reliable SMP hardware was preserved unchanged. The first version of the SMP was ready for the LHC startup in the year 2008. Nevertheless the quality of the SMP firmware was objectionable. There were new requirements and therefore the SMP specification was extended. On that occasion it was decided that the existing SMP firmware will not be continued and that it should be started from scratch. For the new version the firmware implementation should be carried out on the basis of the strictly defined approach, which will ensure high quality and therefore reliability of the SMP. The starting point of the work was the IEC 61508 standard, which was supposed to be matched for the specific needs of the facility carrying out the high energy physics experiments like CERN. As the result of that thesis a full electronic protection system lifecycle was proposed, form the conception through the risk analysis to the implementation and deployment. The method proposed was applied to the critical firmware implementation of the SMP. Examples of the most critical functions realised by the SMP system are shown in the final chapters of the thesis. The second version of the SMP was deployed to be used in the LHC accelerator in the year 2010. Since then it performs its role without failures and therefore it is foreseen to be operated without any changes up to the end of the LHC project. The second result of the thesis is the proposed lifecycle, which can be used for the evaluation of the existing project or for the implementation of the new programmable protection systems for the high energy particle experiments at CERN or in the similar scientific laboratory.
Record ID
WUTf3620872e287407f9279a4741d9a759c
Diploma type
Doctor of Philosophy
Author
Maciej Kwiatkowski Maciej Kwiatkowski,, The Institute of Electronic Systems (FEIT/PE)Faculty of Electronics and Information Technology (FEIT)
Title in Polish
Metody aplikacji programowalnych struktur logicznych w elektronicznych systemach zabezpieczeń akceleratorów cząstek wysokich energii
Title in English
Methods for the Application of Programmable Logic Devices in Electronic Protection Systems for High Energy Particle Accelerators
Language
(en) English
Certifying Unit
Faculty of Electronics and Information Technology (FEIT)
Discipline
electronics / (technology domain) / (technological sciences)
Status
Finished
Start date
02-02-2009
Defense Date
13-02-2014
Title date
25-02-2014
Supervisor
Internal reviewers
Tadeusz Łuba Tadeusz Łuba,, The Institute of Telecommunications (FEIT)Faculty of Electronics and Information Technology (FEIT)
External reviewers
Turała Michał Turała Michał,, Undefined Affiliation
Paweł Gryboś Paweł Gryboś,, Undefined Affiliation
Pages
162
Keywords in English
Electronics, Programmable Logic Devices, Protection Systems, IEC 61508, Particle Accelerators
Abstract in English
The present thesis was realised within the framework of the Doctoral Student programme at the European Organisation for Nuclear Research CERN, which is situated near Geneva. The aim of this thesis was to develop a method for reliable firmware implementation and to use that method to implement a new firmware for the Safe Machine Parameters (SMP) system. That system relies heavily on the Field Programmable Gate Arrays (FPGA) and it is one of the key machine protection systems of the Large Hadron Collider (LHC). The conception of the SMP hardware originates from the fully tested Beam Interlock System (BIS) being a result of another PhD thesis. For that reason the reliable SMP hardware was preserved unchanged. The first version of the SMP was ready for the LHC startup in the year 2008. Nevertheless the quality of the SMP firmware was objectionable. There were new requirements and therefore the SMP specification was extended. On that occasion it was decided that the existing SMP firmware will not be continued and that it should be started from scratch. For the new version the firmware implementation should be carried out on the basis of the strictly defined approach, which will ensure high quality and therefore reliability of the SMP. The starting point of the work was the IEC 61508 standard, which was supposed to be matched for the specific needs of the facility carrying out the high energy physics experiments like CERN. As the result of that thesis a full electronic protection system lifecycle was proposed, form the conception through the risk analysis to the implementation and deployment. The method proposed was applied to the critical firmware implementation of the SMP. Examples of the most critical functions realised by the SMP system are shown in the final chapters of the thesis. The second version of the SMP was deployed to be used in the LHC accelerator in the year 2010. Since then it performs its role without failures and therefore it is foreseen to be operated without any changes up to the end of the LHC project. The second result of the thesis is the proposed lifecycle, which can be used for the evaluation of the existing project or for the implementation of the new programmable protection systems for the high energy particle experiments at CERN or in the similar scientific laboratory.
Thesis file
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Uniform Resource Identifier
https://repo.pw.edu.pl/info/phd/WUTf3620872e287407f9279a4741d9a759c/
URN
urn:pw-repo:WUTf3620872e287407f9279a4741d9a759c

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