Hardware accelerated data analysis methods for information security assurance

Jakub Botwicz

Abstract

Transmission technologies and data storages systems used in recent IT systems are becoming more and more efficient and voluminous. These systems require also more productive data analysis tools. They are necessary to value the usefulness of data, its category or language and also to define data that can be malicious. Currently used processor architectures are very cost efficient but they lack of processing efficiency in specific applications. The main objective of this thesis is to prove the argument that the data analysis process can be aided by hardware implementation architectures like reconfigurable devices. This was achieved by implementing a hardware classification module to classify files of different data types. The prepared module classifies data with an accuracy of 90% with the throughput of 109 Gb/s which is 672 times faster than the same task using a general purpose processor. Furthermore, the classification module uses only 5% of the hardware resources of the biggest currently available reconfigurable chip and only 13% of its input-output pins. This means that by multiplication of this module inside the biggest chip it is possible to achieve even n-times higher throughput. Another important element of this thesis is the description of the data processing flow: from data samples to a source code in a hardware description language that is used to implement the module in a hardware chip. In this way, a bridge was built between artificial intelligence data analysis tools and hardware synthesis tools has been made. So the prepared methods and software can be used to solve various problems in this field. Moreover, a universal framework for security data analysis is presented which consists of a hardware and software synthesis with the pattern matching module, that can be used to detect malicious software.
Diploma typeDoctor of Philosophy
Author Jakub Botwicz (FEIT / IT)
Jakub Botwicz,,
- The Institute of Telecommunications
Title in EnglishHardware accelerated data analysis methods for information security assurance
Languagepl polski
Certifying UnitFaculty of Electronics and Information Technology (FEIT)
Disciplinetelecommunications / (technology domain) / (technological sciences)
Start date25-09-2009
Defense Date18-05-2010
End date25-05-2010
Supervisor Tadeusz Łuba (FEIT / IT)
Tadeusz Łuba,,
- The Institute of Telecommunications

Internal reviewers Marian Andrzej Adamski - [Instytut Informatyki i Elektroniki (IIE) [Wydział Elektrotechniki, Informatyki i Telekomunikacji (WEIiT)]]
Marian Andrzej Adamski,,
-
- Instytut Informatyki i Elektroniki
External reviewers Zbigniew Kotulski (FEIT / IT)
Zbigniew Kotulski,,
- The Institute of Telecommunications
Pages110
Keywords in Englishdata files, reprogrammable, security and communication systems, knowledge acquisition, data classification
Abstract in EnglishTransmission technologies and data storages systems used in recent IT systems are becoming more and more efficient and voluminous. These systems require also more productive data analysis tools. They are necessary to value the usefulness of data, its category or language and also to define data that can be malicious. Currently used processor architectures are very cost efficient but they lack of processing efficiency in specific applications. The main objective of this thesis is to prove the argument that the data analysis process can be aided by hardware implementation architectures like reconfigurable devices. This was achieved by implementing a hardware classification module to classify files of different data types. The prepared module classifies data with an accuracy of 90% with the throughput of 109 Gb/s which is 672 times faster than the same task using a general purpose processor. Furthermore, the classification module uses only 5% of the hardware resources of the biggest currently available reconfigurable chip and only 13% of its input-output pins. This means that by multiplication of this module inside the biggest chip it is possible to achieve even n-times higher throughput. Another important element of this thesis is the description of the data processing flow: from data samples to a source code in a hardware description language that is used to implement the module in a hardware chip. In this way, a bridge was built between artificial intelligence data analysis tools and hardware synthesis tools has been made. So the prepared methods and software can be used to solve various problems in this field. Moreover, a universal framework for security data analysis is presented which consists of a hardware and software synthesis with the pattern matching module, that can be used to detect malicious software.
PKT classification710900 - Teoria telekomunikacji. Zagadnienia podstawowe telekomunikacji
KBN classification35 - telekomunikacja
EU classification8030
Thesis file
doktorat Botwicz.pdf 1.77 MB

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