Self-testing of user-programmed FPGAs

Paweł Tomaszewicz

Abstract

The research project covers the following topics: – development of a representation (model) of user-programmed FPGAs, and a procedure of obtaining such a representation from the output file of a commercial CAD system; – development of a method to analysing a testability of circuit for a pseudoexhaustive testing of combinational blocks, and development of a method for modifying the circuit to enable such blocks intended testing; – development of a method for decomposing a circuit into test blocks that are tested concurrently in test sessions – the method is based on the concept of logic cone and a linear segment; – development of test plan which is controlled by the parameter that describes the maximal length of a test pattern generator; – development of a method to implement BIST logic for each test session; – experimental verification of the proposed methods through the development of a test plan for testing a set of circuits (benchmarks) ISCAS85 and ISCAS89 implemented with an FPGA from Altera’s FLEX10k family.
Diploma typeDoctor of Philosophy
Author Paweł Tomaszewicz (FEIT / IT)
Paweł Tomaszewicz,,
- The Institute of Telecommunications
Title in EnglishSelf-testing of user-programmed FPGAs
Languagepl polski
Certifying UnitFaculty of Electronics and Information Technology (FEIT)
Disciplinetelecommunications / (technology domain) / (technological sciences)
Start date23-03-1999
Defense Date12-06-2001
End date26-06-2001
Supervisor Andrzej Kraśniewski (FEIT / IT)
Andrzej Kraśniewski,,
- The Institute of Telecommunications

Internal reviewers Tadeusz Łuba (FEIT / IT)
Tadeusz Łuba,,
- The Institute of Telecommunications
External reviewers Andrzej Hławiczka
Andrzej Hławiczka,,
-
Pages89
Keywords in Englishself-testing (BIST), programmable digital devices (FPGA, CPLD), digital circuits, testing of integrated circuits, programmable digital structure FPGA
Abstract in English The research project covers the following topics: – development of a representation (model) of user-programmed FPGAs, and a procedure of obtaining such a representation from the output file of a commercial CAD system; – development of a method to analysing a testability of circuit for a pseudoexhaustive testing of combinational blocks, and development of a method for modifying the circuit to enable such blocks intended testing; – development of a method for decomposing a circuit into test blocks that are tested concurrently in test sessions – the method is based on the concept of logic cone and a linear segment; – development of test plan which is controlled by the parameter that describes the maximal length of a test pattern generator; – development of a method to implement BIST logic for each test session; – experimental verification of the proposed methods through the development of a test plan for testing a set of circuits (benchmarks) ISCAS85 and ISCAS89 implemented with an FPGA from Altera’s FLEX10k family.
PKT classification710900 - Teoria telekomunikacji. Zagadnienia podstawowe telekomunikacji
KBN classification35 - telekomunikacja
EU classification8030
Thesis file
Tomaszewicz_Pawel_samotestowanie.pdf 2.57 MB
Citation count*1 (2020-09-22)

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