Optimization of arithmetical algorithms of JVT"s decoder for Equator"s MAP-CA processor architecture

Adam Dawidziuk

Abstract

n/a
Diploma typeMaster of Science
Author Adam Dawidziuk (FEIT / PE)
Adam Dawidziuk,,
- The Institute of Electronic Systems
Title in PolishOptymalizacja operacji arytmetycznych dekodera JVT w architekturze procesora MAP-CA firmy Equator
Supervisor Władysław Skarbek (FEIT / RE)
Władysław Skarbek,,
- The Institute of Radioelectronics

Certifying unitFaculty of Electronics and Information Technology (FEIT)
Affiliation unitThe Institute of Radioelectronics (FEIT / RE)
Languagepl polski
StatusFinished
Issue date (year)2003
Internal identifierENIR-PM.003576

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