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Implementacja układu mnożącego opartego na algorytmie Schonhagego- Strassena w języku VHDL

Grzegorz Zabłocki

Record ID
WUT02670c0d23c446339a4104715ac5f2ee
Diploma type
Master of Science
Author
Grzegorz Zabłocki (FEIT/PE) Grzegorz Zabłocki,, The Institute of Electronic Systems (FEIT/PE)Faculty of Electronics and Information Technology (FEIT)
Supervisor
Tomasz Adamski (FEIT/PE) Tomasz Adamski,, The Institute of Electronic Systems (FEIT/PE)Faculty of Electronics and Information Technology (FEIT)
Certifying unit
Faculty of Electronics and Information Technology (FEIT)
Affiliation unit
The Institute of Electronic Systems (FEIT/PE)
Language
(pl) Polish
Status
Finished
Issue date (year)
2002
Internal identifier
ENSE-PM.001657
Keywords in Polish
MNOŻENIE, IMPLEMENTACJE, VHDL, ALGORYTM SCHONHAGEGO-STRASSENA

Uniform Resource Identifier
https://repo.pw.edu.pl/info/master/WUT02670c0d23c446339a4104715ac5f2ee/
URN
urn:pw-repo:WUT02670c0d23c446339a4104715ac5f2ee

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