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VHDL models of digital blocks for signals defuzzification in the outputs of fuzzy knowledge based controllers

Szymon Wiśniewski

Diploma type
Engineer's / Bachelor of Science
Diploma type
Engineer's thesis
Author
Szymon Wiśniewski (FEIT/MO) Szymon Wiśniewski,, The Institute of Microelectronics and Optoelectronics (FEIT/MO)Faculty of Electronics and Information Technology (FEIT)
Title in Polish
Modele VHDL bloków cyfrowych realizujących różne metody wyostrzania sygnałów wyjściowych sterownika rozmytego
Supervisor
Andrzej Wielgus (FEIT/MO) Andrzej Wielgus,, The Institute of Microelectronics and Optoelectronics (FEIT/MO)Faculty of Electronics and Information Technology (FEIT)
Certifying unit
Faculty of Electronics and Information Technology (FEIT)
Affiliation unit
The Institute of Microelectronics and Optoelectronics (FEIT/MO)
Language
(pl) Polish
Status
Finished
Issue date (year)
2009

Uniform Resource Identifier
https://repo.pw.edu.pl/info/bachelor/WUT8be327cbd05d47aab44acad411633605/
URN
urn:pw-repo:WUT8be327cbd05d47aab44acad411633605

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