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Szybkie i potokowe układy arytmetyczne - Implementacja w układach reprogramowalnych

Mateusz Maniszewski

Diploma type
Engineer's / Bachelor of Science
Diploma type
Engineer's thesis
Author
Mateusz Maniszewski (FEIT) Mateusz Maniszewski,, The Institute of Telecommunications (FEIT)Faculty of Electronics and Information Technology (FEIT)
Supervisor
Piotr Sapiecha (FEIT) Piotr Sapiecha,, The Institute of Telecommunications (FEIT)Faculty of Electronics and Information Technology (FEIT)
Certifying unit
Faculty of Electronics and Information Technology (FEIT)
Affiliation unit
The Institute of Telecommunications (FEIT)
Language
(pl) Polish
Status
Finished
Issue date (year)
2007
Internal identifier
ENIT-PI.002864
Keywords in Polish
UKŁADY ARYTMETYCZNE, FPGA

Uniform Resource Identifier
https://repo.pw.edu.pl/info/bachelor/WUT6505bd8269864312ab12ff23ce117e0d/
URN
urn:pw-repo:WUT6505bd8269864312ab12ff23ce117e0d

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