Ethernet-based slow control system for parallel configuration of FPGA-based front-end boards

Wojciech Zabołotny

Abstract

n/a
Author Wojciech Zabołotny (FEIT / PE)
Wojciech Zabołotny,,
- The Institute of Electronic Systems
Pages068
Book Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018), 2019, Sissa Medialab
DOIDOI:10.22323/1.343.0068
Score (nominal)15
ScoreMinisterial score = 15.0, 26-07-2019, ChapterFromConference
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