A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip
A. Lattuca , G. Mazza , G. Aglieri Rinella , C. Cavicchioli , N. Chanlek , A. Collue , Y. Degerli , A. Dorokhov , C. Flouzat , D. Gajanana , C. Gao , F. Guilloux , Krzysztof Sielewicz
AbstractThis work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 µm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented.
|Total number of authors||38|
|Journal series||Journal of Instrumentation, ISSN 1748-0221|
|Publication size in sheets||0.5|
|Keywords in English||Electronic detector readout concepts (solid-state); Particle tracking detectors (Solidstate detectors)|
|Score|| = 20.0, 27-03-2017, ArticleFromJournal|
= 35.0, 27-03-2017, ArticleFromJournal
|Publication indicators||: 2016 = 1.22 (2) - 2016=1.297 (5)|
* presented citation count is obtained through Internet information analysis and it is close to the number calculated by the Publish or Perish system.