A 10 Gs/s latched comparator with dynamic offset cancellation in 28nm FD-SOI process

Zbigniew Jaworski


This papers presents a high-speed, latched comparator implemented in industrial 28 nm FD-SOI technology. A novel approach to counter the mismatch is proposed. The solution employs trimming the threshold voltage by means of modulating of back-gate polarization of FD-SOI transistors. The comparator is a first step towards the design of a complete 4-bit FLASH analog-to-digital converter, with a sampling frequency of 10 GHz.
Author Zbigniew Jaworski (FEIT / MO)
Zbigniew Jaworski,,
- The Institute of Microelectronics and Optoelectronics
Book Swatowska Barbara, Maziarz Wojciech, Pisarkiewicz Tadeusz, Kucewicz Wojciech (eds.): Proceedings of SPIE Electron Technology Conference 2016, vol. 1, no. 10175, 2016, P.O.Box 10, Bellingham, Washington 98227-0010 USA, SPIE, ISBN 9781510608436, 354 p., DOI:10.1117/12.2270351
Keywords in EnglishPolarization; Transistors
URL http://proceedings.spiedigitallibrary.org/proceeding.aspx?articleid=2595264
Languageen angielski
wut_comp_28nmfdsoi.pdf 701.48 KB
Score (nominal)15
ScoreMinisterial score = 15.0, BookChapterMatConfByIndicator
Ministerial score (2013-2016) = 15.0, BookChapterMatConfByIndicator
Publication indicators Scopus Citations = 1; WoS Citations = 0; GS Citations = 2.0
Citation count*2 (2020-12-16)
Additional fields
Numer pracy101750A
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