A 10 Gs/s latched comparator with dynamic offset cancellation in 28nm FD-SOI process
Zbigniew Jaworski
Abstract
This papers presents a high-speed, latched comparator implemented in industrial 28 nm FD-SOI technology. A novel approach to counter the mismatch is proposed. The solution employs trimming the threshold voltage by means of modulating of back-gate polarization of FD-SOI transistors. The comparator is a first step towards the design of a complete 4-bit FLASH analog-to-digital converter, with a sampling frequency of 10 GHz.| Author | |
| Pages | 1-7 |
| Book | Swatowska Barbara, Maziarz Wojciech, Pisarkiewicz Tadeusz, Kucewicz Wojciech (eds.): Proceedings of SPIE Electron Technology Conference 2016, vol. 1, no. 10175, 2016, P.O.Box 10, Bellingham, Washington 98227-0010 USA, SPIE, ISBN 9781510608436, 354 p., DOI:10.1117/12.2270351 |
| Keywords in English | Polarization; Transistors |
| DOI | DOI:10.1117/12.2263521 |
| URL | http://proceedings.spiedigitallibrary.org/proceeding.aspx?articleid=2595264 |
| Language | en angielski |
| File | |
| Score (nominal) | 15 |
| Score | = 15.0, BookChapterMatConfByIndicator = 15.0, BookChapterMatConfByIndicator |
| Publication indicators | = 1; = 0; = 2.0 |
| Citation count* | 2 (2020-12-16) |
| Additional fields | |
| Numer pracy | 101750A |
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* presented citation count is obtained through Internet information analysis and it is close to the number calculated by the Publish or Perish system.
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