A 10 Gs/s latched comparator with dynamic offset cancellation in 28nm FD-SOI process
AbstractThis papers presents a high-speed, latched comparator implemented in industrial 28 nm FD-SOI technology. A novel approach to counter the mismatch is proposed. The solution employs trimming the threshold voltage by means of modulating of back-gate polarization of FD-SOI transistors. The comparator is a first step towards the design of a complete 4-bit FLASH analog-to-digital converter, with a sampling frequency of 10 GHz.
|Book||Swatowska Barbara, Maziarz Wojciech, Pisarkiewicz Tadeusz, Kucewicz Wojciech (eds.): Proceedings of SPIE Electron Technology Conference 2016, vol. 1, no. 10175, 2016, SPIE, ISBN 9781510608436, 354 p., DOI:10.1117/12.2270351|
|Keywords in English||Polarization; Transistors|
|Score|| = 15.0, 27-03-2017, BookChapterMatConfByIndicator|
= 15.0, 27-03-2017, BookChapterMatConfByIndicator
|Citation count*||1 (2018-01-25)|
* presented citation count is obtained through Internet information analysis and it is close to the number calculated by the Publish or Perish system.