Optimization of the VeSFET Structure Dedicated to Basic Logic Cells in VeSTIC Technology
Mikołaj Pałgan , Andrzej Pfitzner
AbstractThis paper presents a part of feasibility study of VeSTIC (Vertical Slit Transistor-based Integrated Circuit) technology. The goal is an area saving of logic cells designed in this technology by using junction-less VeSFET devices (Vertical-Slit Field-Effect Transistor). Thanks to their feature: two electrically symmetric gates, there is a possibility to greatly reduce the number of elements required to build digital circuits. The use of complementary pair of twin-gate VeSFETs enables to design two-input NOR or NAND cell composed of two instead of four transistors. The combination of the key device parameters: slit width and dopants concentration as well as gate oxide thickness have been established in order to obtain both OR and AND functionality in a single transistor, providing the best distinguishability of the logic states. In particular, we have confirmed that control of the same single bulk channel of VeSFET by two gates ensures to achieve very high drain current ratio (up to le6) corresponding to “11” and “10” input states in the case of the transistor of AND functionality, which is unattainable in other known technologies.
|Publication size in sheets||0.5|
|Book||Napieralski Andrzej (eds.): Proceedings of 25th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2018, vol. CFP18MIX-CDR, 2018, Lodz University of Technology, Department of Microelectronics and Computer Science, ISBN 978-83-63578-13-8, 475 p.|
|project||[PBS1/A3/4/2012_177244] VESTIC – a new manufacturing technology for silicon-based monolithic integrated circuits. Project leader: Kuźmicz Wiesław,
, Phone: (+48) 22 234 7146, application date 16-03-2012, start date 01-01-2012, planned end date 30-11-2015, end date 30-09-2017, IMiO/2012/PBS/3, Completed
|Score|| = 15.0, 20-08-2018, BookChapterMatConfByIndicator|
= 15.0, 20-08-2018, BookChapterMatConfByIndicator
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