Automatic latency equalization in VHDL-implemented complex pipelined systems
AbstractIn the pipelined data processing systems it is very important to ensure that parallel paths delay data by the same number of clock cycles. If that condition is not met, the processing blocks receive data not properly aligned in time and produce incorrect results. Manual equalization of latencies is a tedious and error-prone work. This paper presents an automatic method of latency equalization in systems described in VHDL. The proposed method uses simulation to measure latencies and verify introduced correction. The solution is portable between different simulation and synthesis tools. The method does not increase the complexity of the synthesized design comparing to the solution based on manual latency adjustment. The example implementation of the proposed methodology together with a simple design demonstrating its use is available as an open source project under BSD license.
|Publication size in sheets||0.5|
|Book||Romaniuk Ryszard (eds.): Proc. SPIE. 10031, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2016, vol. 10031, 2016, P.O. Box 10, Bellingham, Washington 98227-0010 USA , SPIE , ISBN 9781510604858, [781510604865 (electronic) ], 1170 p., DOI:10.1117/12.2257157|
|Project||Research on measurement, circuit and signal theory and electronic circuits and systems. Project leader: Starecki Tomasz,
, Phone: +48 22 234 7744; +48 22 234 3657, start date 12-05-2016, end date 31-12-2017, ISE/2016/DS, Completed
|Score|| = 15.0, 10-03-2020, BookChapterMatConfByConferenceseries|
= 15.0, 10-03-2020, BookChapterMatConfByConferenceseries
|Publication indicators||= 2; = 0; = 2.0|
|Citation count*||2 (2020-08-22)|
* presented citation count is obtained through Internet information analysis and it is close to the number calculated by the Publish or Perish system.