CMOS standard cells characterization for open defects for test pattern generation

Andrzej Wielgus , Witold Pleskacz

Abstract

This paper presents an extended method of CMOS standard cells characterization for defect based voltage testing. It allows to estimate the probabilities of physical open defects occurrences in a cell, describes its faulty behavior caused by the defects and finds the test sequences that detect those faults. Finally, the minimal set of test sequences is selected to cover all detectable faults and the optimal complex test sequence is constructed. Experimental results for cells from industrial standard cell library are presented as well.
Author Andrzej Wielgus (FEIT / MO)
Andrzej Wielgus,,
- The Institute of Microelectronics and Optoelectronics
, Witold Pleskacz (FEIT / MO)
Witold Pleskacz,,
- The Institute of Microelectronics and Optoelectronics
Pages1-8
Book Swatowska Barbara, Maziarz Wojciech, Pisarkiewicz Tadeusz, Kucewicz Wojciech (eds.): Proceedings of SPIE Electron Technology Conference 2016, vol. 1, no. 10175, 2016, P.O.Box 10, Bellingham, Washington 98227-0010 USA, SPIE, ISBN 9781510608436, 354 p., DOI:10.1117/12.2270351
Keywords in EnglishCMOS
DOIDOI:10.1117/12.2261887
URL http://proceedings.spiedigitallibrary.org/proceeding.aspx?articleid=2595272
Languageen angielski
Score (nominal)15
ScoreMinisterial score = 15.0, 27-03-2017, BookChapterMatConfByIndicator
Ministerial score (2013-2016) = 15.0, 27-03-2017, BookChapterMatConfByIndicator
Publication indicators Scopus Citations = 0; WoS Citations = 0
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Numer pracy101750I
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