Integer-N phase locked loop for bluetooth receiver in CMOS 130 nm technology
Igor Butryn , Krzysztof Siwiec , Jakub Kopański , Witold Pleskacz
AbstractThe paper presents an Integer-N phase locked loop (PLL) for Bluetooth receiver implemented in CMOS 130 nm technology. The presented phase locked loop consists of an LC quadrature voltage controlled oscillator with capacitor bank, a tri-state phase-frequency detector with charge pump, a third order passive filter and a programmable divider. The PLL has a supply voltage of 1.2 V and dissipates 2.4 mW. The output frequency range of the phase locked loop is from 2.2 GHz to 2.8 GHz and phase noise is equal -124 dBm/Hz at 3 MHz from carrier frequency.
|Publication size in sheets||0.5|
|Book||Brenkus Juraj, Stopjakova Viera (eds.): Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, vol. CFP16DDE-ART, 2016, IEEE Computer Society, ISBN 978-1-5090-2467-4, 260 p.|
|Keywords in English||receiver, Phase locked loop, frequency synthesizer, bluetooth|
|project||xxx. Project leader: Pleskacz Witold,
, Phone: (48 22) 234 53 64, application date 22-03-2013, start date 06-05-2013, planned end date 05-05-2016, DOBR/0053/R/ID1/2013/03, Implemented
|Score|| = 15.0, 27-03-2017, BookChapterMatConf|
= 15.0, 27-03-2017, BookChapterMatConf
|Citation count*||1 (2018-02-19)|
* presented citation count is obtained through Internet information analysis and it is close to the number calculated by the Publish or Perish system.