An FPGA-based reconfigurable DDC algorithm

Bartłomiej Juszczyk , Grzegorz Henryk Kasprowicz


This paper describes implementation of reconfigurable digital down converter in an FPGA structure. System is designed to work with quadrature signals. One of the main criteria of the project was to provied wide range of reconfiguration in order to fullfill various application rage. Potential applications include: software defined radio receiver, passive noise radars and measurement data compression. This document contains general system overview, short description of hardware used in the project and gateware implementation.
Author Bartłomiej Juszczyk (FEIT / PE)
Bartłomiej Juszczyk,,
- The Institute of Electronic Systems
, Grzegorz Henryk Kasprowicz (FEIT / PE)
Grzegorz Henryk Kasprowicz,,
- The Institute of Electronic Systems
Pages 100314Y-1- 100314Y-6
Publication size in sheets0.5
Book Romaniuk Ryszard (eds.): Proc. SPIE. 10031, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2016, vol. 10031, 2016, P.O. Box 10, Bellingham, Washington 98227-0010 USA , SPIE , ISBN 9781510604858, [781510604865 (electronic) ], 1170 p., DOI:10.1117/12.2257157
Keywords in English FPGA, Signal processing, PCIe, measurement system, Digital Downconverter, FIR filter, NCO
Languageen angielski
100314YKasprowicz.pdf 1.8 MB
Score (nominal)15
Score sourceconferenceIndex
ScoreMinisterial score = 15.0, 31-12-2019, BookChapterMatConfByConferenceseries
Ministerial score (2013-2016) = 15.0, 31-12-2019, BookChapterMatConfByConferenceseries
Publication indicators Scopus Citations = 0; WoS Citations = 0
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