An FPGA-based reconfigurable DDC algorithm

Bartłomiej Juszczyk , Grzegorz Henryk Kasprowicz

Abstract

This paper describes implementation of reconfigurable digital down converter in an FPGA structure. System is designed to work with quadrature signals. One of the main criteria of the project was to provied wide range of reconfiguration in order to fullfill various application rage. Potential applications include: software defined radio receiver, passive noise radars and measurement data compression. This document contains general system overview, short description of hardware used in the project and gateware implementation.
Author Bartłomiej Juszczyk ISE
Bartłomiej Juszczyk,,
- The Institute of Electronic Systems
, Grzegorz Henryk Kasprowicz ISE
Grzegorz Henryk Kasprowicz,,
- The Institute of Electronic Systems
Pages 100314Y-1- 100314Y-6
Publication size in sheets0.5
Book Romaniuk Ryszard (eds.): Proc. SPIE. 10031, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2016, vol. 10031, 2016, SPIE , ISBN 9781510604858, [781510604865 (electronic) ], 1170 p., DOI:10.1117/12.2257157
Keywords in English FPGA, Signal processing, PCIe, measurement system, Digital Downconverter, FIR filter, NCO
DOIDOI:10.1117/12.2249318
URL http://dx.doi.org.spiedl.eczyt.bg.pw.edu.pl/10.1117/12.2249318
Languageen angielski
File
100314YKasprowicz.pdf (file archived - login or check accessibility on faculty) 100314YKasprowicz.pdf 1.8 MB
Score (nominal)15
ScoreMinisterial score = 15.0, 27-03-2017, BookChapterMatConf
Ministerial score (2013-2016) = 15.0, 27-03-2017, BookChapterMatConf
Citation count*0
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