An FPGA-based reconfigurable DDC algorithm
Bartłomiej Juszczyk , Grzegorz Henryk Kasprowicz
AbstractThis paper describes implementation of reconﬁgurable digital down converter in an FPGA structure. System is designed to work with quadrature signals. One of the main criteria of the project was to provied wide range of reconﬁguration in order to fullﬁll various application rage. Potential applications include: software deﬁned radio receiver, passive noise radars and measurement data compression. This document contains general system overview, short description of hardware used in the project and gateware implementation.
|Publication size in sheets||0.5|
|Book||Romaniuk Ryszard (eds.): Proc. SPIE. 10031, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2016, vol. 10031, 2016, SPIE , ISBN 9781510604858, [781510604865 (electronic) ], 1170 p., DOI:10.1117/12.2257157|
|Keywords in English||FPGA, Signal processing, PCIe, measurement system, Digital Downconverter, FIR ﬁlter, NCO|
|Score|| = 15.0, 25-09-2019, BookChapterMatConfByConferenceseries|
= 15.0, 25-09-2019, BookChapterMatConfByConferenceseries
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