Effect of inner interface traps on high-k gate stack admittance characteristics

Andrzej Igor Mazurak , Jakub Maciej Jasiński , Bogdan Majkusiak

Abstract

Admittance parameters analysis can give useful information on traps located at the inner interface in high-k gate stacks. The presented study reveals that conductance characteristics are more valuable for characterization procedure then capacitance ones. It particularly considers structures in which tunnel communication via traps cannot be neglected.
Author Andrzej Igor Mazurak IMiO
Andrzej Igor Mazurak,,
- The Institute of Microelectronics and Optoelectronics
, Jakub Maciej Jasiński IMiO
Jakub Maciej Jasiński,,
- The Institute of Microelectronics and Optoelectronics
, Bogdan Majkusiak IMiO
Bogdan Majkusiak,,
- The Institute of Microelectronics and Optoelectronics
Pages194-197
Publication size in sheets0.5
Book Sverdlov Viktor, Selberherr Siegfried, Francisco Gamiz, Cristoloveanu Sorin (eds.): Proceedings of EUROSOI-ULIS 2016, vol. CFP1649D-ART, 2016, IEEE, ISBN 978-1-4673-8609-8, 260 p.
DOIDOI:10.1109/ULIS.2016.7440086
URL http://ieeexplore.ieee.org/document/7440086/
projectxxx. Project leader: Jasiński Jakub Maciej, , Phone: (+48) 22 234 79 07, application date 17-05-2012, start date 18-07-2013, planned end date 17-01-2016, UMO-2012/07/N/ST7/03233, Implemented
WEiTI Projects financed by NSC [Projekty finansowane przez NCN]
xxx. Project leader: Beck Romuald, , Phone: (+48) 22 234 75 34, application date 22-12-2011, start date 30-08-2012, planned end date 29-08-2015, IMiO/2011/NCN/5, Implemented
WEiTI Projects financed by NSC [Projekty finansowane przez NCN]
Languageen angielski
Score (nominal)15
ScoreMinisterial score = 15.0, 29-01-2018, BookChapterMatConf
Ministerial score (2013-2016) = 15.0, 29-01-2018, BookChapterMatConf
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