Contribution to scaling of Vertical-Slit Field-Effect Transistor (VeSFET)

Andrzej Pfitzner , Beata Kowalska


A Junction-less twin-gate Vertical-Slit Field-Effect Transistor (VeSFET) is the elementary component of a new 3D VeSTIC technology [1]. Feasibility studies conducted until now indicate that VeSTIC architecture has the potential to overcome many barriers of ICs scaling in the deep-submicron era. As it was shown earlier, electrical properties of VeSFETs seems to be very attractive, but simulations [5] indicate different correlations between electrical and structure parameters in comparison with those of MOSFETs which operate in inversion mode. In this paper the exploration of the VeSFET parameters space has been developed and preliminary scaling recommendations are formulated.
Author Andrzej Pfitzner IMiO
Andrzej Pfitzner,,
- The Institute of Microelectronics and Optoelectronics
, Beata Kowalska IMiO
Beata Kowalska,,
- The Institute of Microelectronics and Optoelectronics
Publication size in sheets0.5
Book Napieralski Andrzej (eds.): Proceedings of 23rd International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2016, vol. CFP16MIX-CDR, 2016, Lodz University of Technology, Department of Microelectronics and Computer Science, ISBN 978-83-63578-08-4, 538 p.
Keywords in EnglishVeSFET; VeSTIC technology; Vertical-Slit Field-Effect Transistor; junction-less transistor; scaling; twin-gate transistor
projectVESTIC – a new manufacturing technology for silicon-based monolithic integrated circuits. Project leader: Kuźmicz Wiesław, , Phone: (+48) 22 234 7146, application date 16-03-2012, start date 01-01-2012, planned end date 30-11-2015, IMiO/2012/PBS/3, Implemented
WEiTI Projects financed by NCRD [Projekty finansowane przez NCBiR (NCBR)]
Languageen angielski
Score (nominal)15
ScoreMinisterial score = 15.0, 27-03-2017, BookChapterMatConfByIndicator
Ministerial score (2013-2016) = 15.0, 27-03-2017, BookChapterMatConfByIndicator
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