Defect Oriented Fault Coverage of 100% Stuck-At Fault Test Sets

M. Blyzniuk , T. Cibakova , Elena Gramatova , Wiesław Kuźmicz , Mykhaylo Lobur , Witold Pleskacz , Jaan Raik , R. Ubar

Abstract

A new fault model is developed for estimation of the coverage of physical defects by hierarchical defect simulation. At the higher level simulation we use the functional fault model, at the lower level we use the defect/fault relationships in the form of defect coverage table and the conditional defect probabilities. A description and the experimental data are given about probabilistic analysis of a complex CMOS gate. Analysis of the quality of 100% stuck-at fault test sets for two benchmark circuits in covering physical defects like internal shorts, stuck-open and stuckon. It has been shown that in the worse case a test with 100% stuck-at fault coverage may have only 47% coverage for internal shorts in complex CMOS gates. It has been shown also that classical test coverage calculation based on counting of defects detected without taking into account the defect probabilities may lead to considerable overestimation of results.
Author M. Blyzniuk
M. Blyzniuk,,
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, T. Cibakova
T. Cibakova,,
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, Elena Gramatova
Elena Gramatova,,
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, Wiesław Kuźmicz (FEIT / MO)
Wiesław Kuźmicz,,
- The Institute of Microelectronics and Optoelectronics
, Mykhaylo Lobur - Lviv Polytechnic National University
Mykhaylo Lobur,,
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, Witold Pleskacz (FEIT / MO)
Witold Pleskacz,,
- The Institute of Microelectronics and Optoelectronics
, Jaan Raik
Jaan Raik,,
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, R. Ubar
R. Ubar,,
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Pages511-516
Publication size in sheets0.5
Book Napieralski Andrzej (eds.): Proceedings of the 7th International Conference: Mixed Design of Integrated Circuits and Systems MIXDES 2000, 2000, Łódź, Poland, Technical University of Łódź, ISBN 83-87202-37-1, 592 p.
Languageen angielski
Score (nominal)0
Publication indicators GS Citations = 10.0
Citation count*10 (2020-09-15)
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