Back-end and interface implementation of the STS-XYTER2 prototype ASIC for the CBM experiment
K. Kasiński , R. Szczygiel , Wojciech Zabołotny
AbstractEach front-end readout ASIC for the High-Energy Physics experiments requires robust and effective hit data streaming and control mechanism. A new STS-XYTER2 full-size prototype chip for the Silicon Tracking System and Muon Chamber detectors in the Compressed Baryonic Matter experiment at Facility for Antiproton and Ion Research (FAIR, Germany) is a 128-channel time and amplitude measuring solution for silicon microstrip and gas detectors. It operates at 250 kHit/s/channel hit rate, each hit producing 27 bits of information (5-bit amplitude, 14-bit timestamp, position and diagnostics data). The chip back-end implements fast front-end channel read-out, timestamp-wise hit sorting, and data streaming via a scalable interface implementing the dedicated protocol (STS-HCTSP) for chip control and hit transfer with data bandwidth from 9.7 MHit/s up to 47 MHit/s. It also includes multiple options for link diagnostics, failure detection, and throttling features. The back-end is designed to operate with the data acquisition architecture based on the CERN GBTx transceivers. This paper presents the details of the back-end and interface design and its implementation in the UMC 180 nm CMOS process.
|Journal series||Journal of Instrumentation, ISSN 1748-0221|
|Publication size in sheets||0.5|
|Keywords in English||Digital electronic circuits; Detector control systems (detector and experiment moni- toring and slow-control systems, architecture, hardware, algorithms, databases); Data acquisition circuits|
|Score|| = 20.0, 27-03-2017, ArticleFromJournal|
= 35.0, 27-03-2017, ArticleFromJournal
|Publication indicators||: 2016 = 1.22 (2) - 2016=1.297 (5)|
|Citation count*||6 (2018-01-23)|
* presented citation count is obtained through Internet information analysis and it is close to the number calculated by the Publish or Perish system.