Self-Testing of FPGA Delay Faults in the System Environment

Andrzej Kraśniewski

Abstract

We propose a procedure for self-testing of an FPGA programmed to implement a user-defined function. The procedure is intended to improve the detectability of FPGA delay faults. This improvement is obtained by modifying the functions of LUTs in the section under test, so that each LUT implements a XOR function. We show that, despite many potential problems, the proposed modification can significantly enhance the susceptibility of FPGA delay faults to random testing.
Author Andrzej Kraśniewski (FEIT / IT)
Andrzej Kraśniewski,,
- The Institute of Telecommunications
Book Proceedings of the 6th IEEE International On-Line Testing Workshop, 2000, IEEE, ISBN 0-7695-0646-1, 220 p.
DOIDOI:10.1109/OLT.2000.856610
Languageen angielski
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2000 Krasniewski Self-Testing of FPGA.pdf 187.79 KB
Score (nominal)0
Publication indicators GS Citations = 6.0
Citation count*6 (2015-04-26)
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