Effect of traps-to-gate tunnel communication on C-V characteristics of MIS capacitors
Andrzej Igor Mazurak , Jakub Maciej Jasiński , Bogdan Majkusiak
The admittance measurements are commonly used for extraction of parameters of the traps located in the gate stack of the metal-insulator-semiconductor structures. The extraction procedures are based on models of the MIS structure, which are usually based on a modified Nicollian-Brews' equivalent circuit but do not comprise charge communication between the traps and the gate electrode. The model proposed in this work includes the traps-to gate tunnel communication and is used to discuss its impact on the capacitance-voltage characteristics of a MIS capacitor with a double-layer insulator gate stack.
|Journal series||Microelectronic Engineering, ISSN 0167-9317, (N/A 70 pkt)|
|No||15 July 2019|
|Publication size in sheets||0.5|
|ASJC Classification||; ; ; ;|
|project||xxx. Project leader: Beck Romuald,
, Phone: (+48) 22 234 75 34, application date 22-12-2011, start date 30-08-2012, planned end date 29-08-2015, IMiO/2011/NCN/5, Implemented
[V4-Japan/01/NaMSeN/02/2015 POLON] Nanophotonics with metal – group-IV-semiconductor nanocomposites: From single nanoobjects to functional ensembles. Project leader: Beck Romuald, , Phone: (+48) 22 234 75 34, application date 29-09-2015, start date 01-02-2016, planned end date 31-01-2019, IMIO/2016/Japan, Implemented
|Score||= 70.0, 08-10-2019, ArticleFromJournal|
|Publication indicators||= 0; = 0; : 2016 = 0.999; : 2017 = 2.02 (2) - 2017=1.461 (5)|
* presented citation count is obtained through Internet information analysis and it is close to the number calculated by the Publish or Perish system.