Comparison of Memory Effect with Voltage or Current Charging Pulse Bias in MIS Structures Based on Codoped Si-NCs Embedded in SiO2 or HfOx
Andrzej Igor Mazurak , Robert Paweł Mroczyński
AbstractCo-doped Si-NCs have been introduced into MIS structures gate dielectric layers. The fabricated test devices were characterized by means of stress-and-sense measurements in terms of device capacitance, flat-band voltage shift, and retention time. Comparison between results for HfOx and SiO2 gate dielectric layers is shown and discussed. Presented findings are promising for possible applications of Si-NCs in memory structures.
|Journal series||Solid-State Electronics, ISSN 0038-1101|
|Vol||21 March 2019|
|Publication size in sheets||0.5|
|Keywords in English||silicon nanocrystal; memory; metal-insulator semiconductor structure; electrical characterization; high-k dielectric|
|ASJC Classification||; ; ;|
|Project||[V4-Japan/01/NaMSeN/02/2015 POLON] Nanophotonics with metal – group-IV-semiconductor nanocomposites: From single nanoobjects to functional ensembles. Project leader: Beck Romuald,
, Phone: (+48) 22 234 75 34, application date 29-09-2015, start date 01-02-2016, planned end date 31-01-2019, IMIO/2016/Japan, Implemented
|Score||= 70.0, 22-06-2020, ArticleFromJournal|
|Publication indicators||= 1; = 0; = 1.0; : 2017 = 0.923; : 2018 = 1.492 (2) - 2018=1.401 (5)|
|Citation count*||1 (2020-08-07)|
* presented citation count is obtained through Internet information analysis and it is close to the number calculated by the Publish or Perish system.