Comparison of Memory Effect with Voltage or Current Charging Pulse Bias in MIS Structures Based on Codoped Si-NCs Embedded in SiO2 or HfOx

Andrzej Igor Mazurak , Robert Paweł Mroczyński


Co-doped Si-NCs have been introduced into MIS structures gate dielectric layers. The fabricated test devices were characterized by means of stress-and-sense measurements in terms of device capacitance, flat-band voltage shift, and retention time. Comparison between results for HfOx and SiO2 gate dielectric layers is shown and discussed. Presented findings are promising for possible applications of Si-NCs in memory structures.
Author Andrzej Igor Mazurak (FEIT / MO)
Andrzej Igor Mazurak,,
- The Institute of Microelectronics and Optoelectronics
, Robert Paweł Mroczyński (FEIT / MO)
Robert Paweł Mroczyński,,
- The Institute of Microelectronics and Optoelectronics
Journal seriesSolid-State Electronics, ISSN 0038-1101, (A 20 pkt)
Issue year2019
Vol21 March 2019
Noin prerss
Publication size in sheets0.5
Keywords in Englishsilicon nanocrystal; memory; metal-insulator semiconductor structure; electrical characterization; high-k dielectric
ASJC Classification2505 Materials Chemistry; 2208 Electrical and Electronic Engineering; 3104 Condensed Matter Physics; 2504 Electronic, Optical and Magnetic Materials
project[V4-Japan/01/NaMSeN/02/2015 POLON] Nanophotonics with metal – group-IV-semiconductor nanocomposites: From single nanoobjects to functional ensembles. Project leader: Beck Romuald, , Phone: (+48) 22 234 75 34, application date 29-09-2015, start date 01-02-2016, planned end date 31-01-2019, IMIO/2016/Japan, Implemented
WEiTI Projekty finansowane przez MNiSW
Languageen angielski
Score (nominal)20
ScoreMinisterial score = 20.0, 17-07-2019, ArticleFromJournal
Publication indicators Scopus Citations = 0; WoS Citations = 0; Scopus SNIP (Source Normalised Impact per Paper): 2017 = 0.923; WoS Impact Factor: 2017 = 1.666 (2) - 2017=1.577 (5)
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