CMOS FD-SOI Technology in the Eyes of a Circuit Designer

Wiesław Kuźmicz


FD-SOI CMOS (Fully Depleted Silion-on-Insulator CMOS) is a technology that attempts to overcome one of the barriers in downscaling of CMOS circuits beyond 28 nm, namely the static power consumption. FD-SOI competes with FinFET technology, and has many advantages. This talk presents FD-SOI technology as seen by a VLSI circuit designer, discussing in more detail a unique advantage of this technology, namely wide range of back bias voltages that allow to control the power consumption and performance by adjusting the threshold voltages. Other advantages for digital and analog design are also discussed, and illustrated by examples of practical designs.
Author Wiesław Kuźmicz (FEIT / MO)
Wiesław Kuźmicz,,
- The Institute of Microelectronics and Optoelectronics
Publication size in sheets0.3
Book Napieralski Andrzej (eds.): Book of Abstracts of 23rd International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2016, 2016, Wólczańska 221/223, 90-924 Łódź, Poland, Lodz University of Technology, Department of Microelectronics and Computer Science, 155 p.
MIXDES2016_BoA.pdf / 59.62 MB / No licence information
Keywords in EnglishFD-SOI; MOS transistor; CMOS; analog circuits; digital circuits
ProjectTHIN but Great Silicon 2 Design Objects. Project leader: Kuźmicz Wiesław, , Phone: (+48) 22 234 7146, application date 12-09-2013, start date 01-01-2014, planned end date 31-12-2017, end date 30-06-2018, IMiO/2014/ENIAC/1, Completed
Languageen angielski
Score (nominal)15
ScoreMinisterial score = 15.0, 04-09-2019, BookChapterMatConfByIndicator
Ministerial score (2013-2016) = 15.0, 04-09-2019, BookChapterMatConfByIndicator
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