A Compact Model of VES-BJT Device

Wiesław Kuźmicz , Piotr Konrad Mierzwiński


VES-BJT is a bipolar transistor fabricated in the VESTIC technology. Its physical structure differs from other state-of-the-art bipolar transistors: its emitter and collector junctions are not plane-parallel, its base is uniformly doped and the emitter and collector regions are identical. In this paper it is shown how to estimate theoretically the most important parameters of its compact model. Comparison with results of numerical simulation is included, advantages and shortcomings of VES-BJT are discussed.
Author Wiesław Kuźmicz (FEIT / MO)
Wiesław Kuźmicz,,
- The Institute of Microelectronics and Optoelectronics
, Piotr Konrad Mierzwiński (FEIT / MO)
Piotr Konrad Mierzwiński,,
- The Institute of Microelectronics and Optoelectronics
Book Napieralski Andrzej (eds.): Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems MIXDES, 2013 , vol. CFP13MIX-PRT, 2013, USA, IEEE Xplore Digital Library, ISBN 978-83-63578-01-5, 625 p.
Keywords in EnglishVESTIC, bipolar transistor, compact model
Languageen angielski
Score (nominal)15
Score sourceconferenceIndex
ScoreMinisterial score = 10.0, 05-06-2020, BookChapterMatConfByIndicator
Ministerial score (2013-2016) = 15.0, 05-06-2020, BookChapterMatConfByIndicator
Publication indicators WoS Citations = 2; GS Citations = 2.0
Citation count*2 (2020-09-07)
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