A Compact Model of VES-BJT Device
Wiesław Kuźmicz , Piotr Konrad Mierzwiński
AbstractVES-BJT is a bipolar transistor fabricated in the VESTIC technology. Its physical structure differs from other state-of-the-art bipolar transistors: its emitter and collector junctions are not plane-parallel, its base is uniformly doped and the emitter and collector regions are identical. In this paper it is shown how to estimate theoretically the most important parameters of its compact model. Comparison with results of numerical simulation is included, advantages and shortcomings of VES-BJT are discussed.
|Book||Napieralski Andrzej (eds.): Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems MIXDES, 2013 , vol. CFP13MIX-PRT, 2013, USA, IEEE Xplore Digital Library, ISBN 978-83-63578-01-5, 625 p.|
|Keywords in English||VESTIC, bipolar transistor, compact model|
|Score|| = 10.0, 05-06-2020, BookChapterMatConfByIndicator|
= 15.0, 05-06-2020, BookChapterMatConfByIndicator
|Publication indicators||= 2; = 2.0|
|Citation count*||2 (2020-09-07)|
* presented citation count is obtained through Internet information analysis and it is close to the number calculated by the Publish or Perish system.