High performance FPGA-based implementation of a parallel multiplier-accumulator

Marek Ciepłucha

Abstract

This paper presents an FPGA-based design and implementation of a universal multiplier-accumulator unit. The proposed structure is based on an idea of parallel multiplication of properly aligned data stored in FPGA on-chip memory used as a cyclic buffer. The example application was implemented in Altera Cyclone II device and worked as a hardware accelerator of digital FIR filter. The results show that the higher performance for high-order FIR filter operation may be achieved in Altera Cyclone II family FPGAs in comparison to modern digital signal processors.
Author Marek Ciepłucha (FEIT / MO)
Marek Ciepłucha ,,
- The Institute of Microelectronics and Optoelectronics
Pages485-489
Book Napieralski Andrzej (eds.): Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems MIXDES, 2013 , vol. CFP13MIX-PRT, 2013, USA, IEEE Xplore Digital Library, ISBN 978-83-63578-01-5, 625 p.
URL http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6613401&tag=1
Languageen angielski
Score (nominal)15
ScoreMinisterial score = 10.0, BookChapterMatConfByIndicator
Ministerial score (2013-2016) = 15.0, BookChapterMatConfByIndicator
Citation count*2 (2016-05-13)
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