High performance FPGA-based implementation of a parallel multiplier-accumulator
- Marek Ciepłucha
This paper presents an FPGA-based design and implementation of a universal multiplier-accumulator unit. The proposed structure is based on an idea of parallel multiplication of properly aligned data stored in FPGA on-chip memory used as a cyclic buffer. The example application was implemented in Altera Cyclone II device and worked as a hardware accelerator of digital FIR filter. The results show that the higher performance for high-order FIR filter operation may be achieved in Altera Cyclone II family FPGAs in comparison to modern digital signal processors.
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- Napieralski Andrzej Andrzej Napieralski (eds.): Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems MIXDES, 2013 , vol. CFP13MIX-PRT, 2013, USA, IEEE Xplore Digital Library, 625 p., ISBN 978-83-63578-01-5
- http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6613401&tag=1 Opening in a new tab
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