Feasibility Studies of EEPROM Memory Implementations in VeSTIC Technology

Bartosz Dec , Andrzej Pfitzner

Abstract

This paper reports a preliminary feasibility study of non-volatile semiconductor memories in VeSTIC technology (Vertical Slit Transistor-based Integrated Circuits). The basic concept of this technology, invented over a decade ago, is a novel 3D architecture, which enables high regularity of the circuit layout and is 3D integration ready. Between evenly distributed vertical pillars, being electrical contacts going all the way through the device layer, all kinds of transistors can be fabricated, and integration of logic components in canvas of density characteristic for memories is accessible. Based on numerical simulations we indicated feasibility of certain EEPROM implementations in VESTICs.
Author Bartosz Dec (FEIT / MO)
Bartosz Dec,,
- The Institute of Microelectronics and Optoelectronics
, Andrzej Pfitzner (FEIT / MO)
Andrzej Pfitzner,,
- The Institute of Microelectronics and Optoelectronics
Pages275-279
Publication size in sheets0.5
Book Napieralski Andrzej (eds.): Proceedings of 25th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2018, vol. CFP18MIX-CDR, 2018, Lodz University of Technology, Department of Microelectronics and Computer Science, ISBN 978-83-63578-13-8, 475 p.
DOIDOI:10.23919/MIXDES.2018.8436679
URL https://ieeexplore.ieee.org/document/8436679/
project[PBS1/A3/4/2012_177244] VESTIC – a new manufacturing technology for silicon-based monolithic integrated circuits. Project leader: Kuźmicz Wiesław, , Phone: (+48) 22 234 7146, application date 16-03-2012, start date 01-01-2012, planned end date 30-11-2015, end date 30-09-2017, IMiO/2012/PBS/3, Completed
WEiTI Projects financed by NCRD [Projekty finansowane przez NCBiR (NCBR)]
Languageen angielski
Score (nominal)15
ScoreMinisterial score = 15.0, 20-08-2018, BookChapterMatConfByIndicator
Ministerial score (2013-2016) = 15.0, 20-08-2018, BookChapterMatConfByIndicator
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