Dual-Metastability FPGA-Based True Random Number Generator

Piotr Z. Wieczorek

Abstract

A novel concept of a true random number generator (TNRG) based on two metastable flip-flops in a FPGA circuit is introduced. Most of metastable based TRNG solutions are based on the assumption of a D-latch (flip-flop) state's uncertainty which is the source of randomness. In the proposed approach direct proximity of the metastable point is not necessary. Difference of the time of response of a pair of nearly metastable flip-flops lies upon the proposed circuit's principle of operation. It can be implemented in common programmable FPGA or CPLD circuits ensuring randomness quality-passing NIST, Diehard and Matlab tests
Author Piotr Z. Wieczorek (FEIT / PE)
Piotr Z. Wieczorek,,
- The Institute of Electronic Systems
Journal seriesElectronics Letters, ISSN 0013-5194
Issue year2013
Vol49
No12
Pages744-745
Publication size in sheets0.3
Keywords in English flip-flops; random number generation; field programmable gate arrays
ASJC Classification2208 Electrical and Electronic Engineering
DOIDOI:10.1049/el.2012.4126
URL http://digital-library.theiet.org/content/journals/10.1049/el.2012.4126
Languageen angielski
File
ELL-2012-4126-PROOF.pdf 335.44 KB
Score (nominal)25
Score sourcejournalList
ScoreMinisterial score = 25.0, 18-08-2020, ArticleFromJournal
Ministerial score (2013-2016) = 25.0, 18-08-2020, ArticleFromJournal
Publication indicators WoS Citations = 11; Scopus Citations = 11; GS Citations = 17.0; Scopus SNIP (Source Normalised Impact per Paper): 2013 = 1.102; WoS Impact Factor: 2013 = 1.068 (2) - 2013=1.03 (5)
Citation count*17 (2020-08-20)
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* presented citation count is obtained through Internet information analysis and it is close to the number calculated by the Publish or Perish system.
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