FPGA Based Fast Synchronous Serial Multi-Wire Links Synchronization

Krzysztof Poźniak

Abstract

The paper debates synchronization method of multi-wire, serial link of constant latency, by means of pseudo-random numbers generators. The solution was designed for various families of FPGA circuits. There were debated synchronization algorithm and functional structure of parameterized transmitter and receiver modules. The modules were realized in VHDL language in a behavioral form.
Author Krzysztof Poźniak (FEIT / PE)
Krzysztof Poźniak,,
- The Institute of Electronic Systems
Pages89032D-1-89032D-10
Book Romaniuk Ryszard (eds.): Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2013, vol. 8903, 2013, SPIE P.O. Box 10, Bellingham, Washington 98227-0010 USA , SPIE, ISBN 9780819497857, [ISSN 0277-786X ], 410 p., DOI:10.1117/12.2049644
Keywords in Englishfast serial link, multi-wire link, data transmission, synchronization, FPGA, VHDL, Altera, Xilinx
DOIDOI:10.1117/12.2036183
Languageen angielski
Score (nominal)15
Score sourceconferenceIndex
ScoreMinisterial score = 10.0, 29-08-2020, BookChapterMatConfByIndicator
Ministerial score (2013-2016) = 15.0, 29-08-2020, BookChapterMatConfByIndicator
Publication indicators Scopus Citations = 6; WoS Citations = 0; GS Citations = 3.0
Citation count*3 (2020-09-15)
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* presented citation count is obtained through Internet information analysis and it is close to the number calculated by the Publish or Perish system.
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