Instruction driven CPU in the FPGA structure
Krzysztof Gracki , Marek Pawłowski , Andrzej Skorupski , Zbigniew Szymański
AbstractThe paper presents the design of processors embedded in an FPGA structure. The type of processor is determined by the preset instruction list. Each instruction is implemented as one functional block attached to a common bus. The processor contains two additional blocks: one contains a common register block and second is responsible for the fetch of the instruction from the program memory. To design the processor, one can choose the instruction set from the library of instructions components. The library is a set of VHDL descriptions of all possible instructions.
|Journal series||Measurement Automation Monitoring, ISSN 2450-2855 [0032-4140]|
|Publication size in sheets||0.3|
|Keywords in English||processor, FPGA systems, VHDL language|
|project||Development of new algorithms in the areas of software and computer architecture, artificial intelligence and information systems and computer graphics . Project leader: Rybiński Henryk,
, Phone: +48 22 234 7731, start date 18-05-2015, end date 30-11-2016, II/2015/DS/1, Completed
|License||Journal (articles only); author's original; ; after publication|
|Score|| = 11.0, 27-03-2017, ArticleFromJournal|
= 11.0, 27-03-2017, ArticleFromJournal
|Citation count*||0 (2018-06-18)|
* presented citation count is obtained through Internet information analysis and it is close to the number calculated by the Publish or Perish system.