Instruction driven CPU in the FPGA structure

Krzysztof Gracki , Marek Pawłowski , Andrzej Skorupski , Zbigniew Szymański


The paper presents the design of processors embedded in an FPGA structure. The type of processor is determined by the preset instruction list. Each instruction is implemented as one functional block attached to a common bus. The processor contains two additional blocks: one contains a common register block and second is responsible for the fetch of the instruction from the program memory. To design the processor, one can choose the instruction set from the library of instructions components. The library is a set of VHDL descriptions of all possible instructions.
Author Krzysztof Gracki (FEIT / IN)
Krzysztof Gracki,,
- The Institute of Computer Science
, Marek Pawłowski (FEIT / IN)
Marek Pawłowski,,
- The Institute of Computer Science
, Andrzej Skorupski (FEIT / IN)
Andrzej Skorupski,,
- The Institute of Computer Science
, Zbigniew Szymański (FEIT / IN)
Zbigniew Szymański,,
- The Institute of Computer Science
Journal seriesMeasurement Automation Monitoring, [Pomiary Automatyka Kontrola], ISSN 2450-2855, [0032-4140]
Issue year2016
Publication size in sheets0.3
Keywords in Englishprocessor, FPGA systems, VHDL language
ProjectDevelopment of new algorithms in the areas of software and computer architecture, artificial intelligence and information systems and computer graphics . Project leader: Rybiński Henryk, , Phone: +48 22 234 7731, start date 18-05-2015, end date 30-11-2016, II/2015/DS/1, Completed
WEiTI Działalność statutowa
Languageen angielski
LicenseJournal (articles only); author's original; Uznanie Autorstwa (CC-BY); after publication
artykuł-KG_MP_AS_ZS.pdf 652.12 KB
Score (nominal)11
Score sourcejournalList
ScoreMinisterial score = 11.0, 02-02-2020, ArticleFromJournal
Ministerial score (2013-2016) = 11.0, 02-02-2020, ArticleFromJournal
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