Nanostructures applied to bit-cell devices

Andrzej Kołodziej , Lidia Łukasiak , Michał Kołodziej


In this work split-gate charge trap FLASH memory with a storage layer containing 3D nano-crystals is proposed and compared with existing sub-90 nm solutions. We estimate electrical properties, cell operations and reliability issues. Analytical predictions show that for nano-crystals with the diameter < 3 nm metals could be the preferred material. The presented 3D layers were fabricated in a CMOS compatible process. We also show what kinds of nano-crystal geometries and distributions could be achieved. The study shows that the proposed memory cells have very good program/erase/read characteristics approaching those of SONOS cells but better retention time than standard discrete charge storage cells. Also dense nano-crystal structure should allow 2-bits of information to be stored.
Author Andrzej Kołodziej - [AGH University of Science and Technology (AGH)]
Andrzej Kołodziej,,
- Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie
, Lidia Łukasiak (FEIT / MO)
Lidia Łukasiak,,
- The Institute of Microelectronics and Optoelectronics
, Michał Kołodziej - AGH University of Science and Technology (AGH) [AGH University of Science and Technology (AGH)]
Michał Kołodziej,,
- Akademia Górniczo-Hutnicza
Publication size in sheets0.5
Book Szczepański Paweł, Kisiel Ryszard, Romaniuk Ryszard (eds.): Proceedings of SPIE Electron Technology Conference 2013, vol. 1, no. 8902, 2013, P.O.Box 10, Bellingham, Washington 98227-0010 USA, SPIE, ISBN 9780819495211, 752 p., DOI:10.1117/12.2033297
Keywords in EnglishFlash memory, MOSFETs, split-gate, SONOS, nano-crystal, charge trap
Languageen angielski
Score (nominal)15
Score sourceconferenceIndex
ScoreMinisterial score = 10.0, 24-01-2020, BookChapterMatConfByIndicator
Ministerial score (2013-2016) = 15.0, 24-01-2020, BookChapterMatConfByIndicator
Publication indicators Scopus Citations = 0; WoS Citations = 0
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