Resistive shorts characterization in CMOS standard cells for test pattern generation
Andrzej Wielgus , Bartosz Potrykus
AbstractThis paper presents an extended method of CMOS standard cells characterization for defect based voltage testing. Resistance of a short defect is taken into account while considering faulty behavior caused by this defect and finding the test vectors that detect this fault. Finally, all of found vectors are validated to check their effectiveness in fault covering and the optimal test sequence for all detectable faults is constructed. Experimental results for cells from industrial standard cell library are presented.
|Book||Szczepański Paweł, Kisiel Ryszard, Romaniuk Ryszard (eds.): Proceedings of SPIE Electron Technology Conference 2013, vol. 1, no. 8902, 2013, P.O.Box 10, Bellingham, Washington 98227-0010 USA, SPIE, ISBN 9780819495211, 752 p., DOI:10.1117/12.2033297|
|Keywords in English||defect based testing, resistive bridging faults, standard cells charakterization|
|Score|| = 10.0, BookChapterMatConfByIndicator|
= 15.0, BookChapterMatConfByIndicator
|Publication indicators||= 1; = 1.0; = 0|
|Citation count*||1 (2020-08-20)|
* presented citation count is obtained through Internet information analysis and it is close to the number calculated by the Publish or Perish system.