Resistive shorts characterization in CMOS standard cells for test pattern generation

Andrzej Wielgus , Bartosz Potrykus

Abstract

This paper presents an extended method of CMOS standard cells characterization for defect based voltage testing. Resistance of a short defect is taken into account while considering faulty behavior caused by this defect and finding the test vectors that detect this fault. Finally, all of found vectors are validated to check their effectiveness in fault covering and the optimal test sequence for all detectable faults is constructed. Experimental results for cells from industrial standard cell library are presented.
Author Andrzej Wielgus (FEIT / MO)
Andrzej Wielgus,,
- The Institute of Microelectronics and Optoelectronics
, Bartosz Potrykus - [Warsaw University of Technology (PW)]
Bartosz Potrykus,,
-
- Politechnika Warszawska
Pages1-7
Book Szczepański Paweł, Kisiel Ryszard, Romaniuk Ryszard (eds.): Proceedings of SPIE Electron Technology Conference 2013, vol. 1, no. 8902, 2013, P.O.Box 10, Bellingham, Washington 98227-0010 USA, SPIE, ISBN 9780819495211, 752 p., DOI:10.1117/12.2033297
Keywords in Englishdefect based testing, resistive bridging faults, standard cells charakterization
DOIDOI:10.1117/12.2031300
URL http://spie.org/x648.xml?product_id=2031300
Languageen angielski
Score (nominal)15
ScoreMinisterial score = 10.0, BookChapterMatConfByIndicator
Ministerial score (2013-2016) = 15.0, BookChapterMatConfByIndicator
Publication indicators Scopus Citations = 1; GS Citations = 1.0; WoS Citations = 0
Citation count*1 (2020-08-20)
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* presented citation count is obtained through Internet information analysis and it is close to the number calculated by the Publish or Perish system.
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