Encryption Using Reconfigurable Reversible Logic Gate and Its Simulation in FPGAs

Marcin Bryk , Krzysztof Gracki , Paweł Kerntopf , Marek Pawłowski , Andrzej Skorupski


Recently an approach to encryption/decryption based on using reversible logic circuits has been proposed. The reason for this is that conventional microelectronic technologies are reaching their limits. On the other hand, reversible logic circuits can decrease energy dissipation theoretically to zero. This paper presents a solution to designing encryption schemes based entirely on reversible logic. In our solution a building block of an encryption scheme is a cascade of 4-input reversible gates. In this way the building block can perform any reversible 4-variable function. For this purpose a reconfigurable reversible gate has been proposed. The design of such a reconfigurable gate built from standard reversible gates, i.e. NOT, CNOT, Toffoli and Fredkin gates, is presented. In the paper a complete scheme for encryption/decryption of 8-bit data is described using VHDL language and its quantum cost is calculated. Simulation and verification of this scheme in FPGAs conclude the paper.
Author Marcin Bryk II
Marcin Bryk,,
- The Institute of Computer Science
, Krzysztof Gracki II
Krzysztof Gracki,,
- The Institute of Computer Science
, Paweł Kerntopf II - [Uniwersytet Łódzki, Wydział Fizyki i Informatyki Stosowanej]
Paweł Kerntopf,,
- The Institute of Computer Science
- Uniwersytet Łódzki, Wydział Fizyki i Informatyki Stosowanej
, Marek Pawłowski II
Marek Pawłowski,,
- The Institute of Computer Science
, Andrzej Skorupski II
Andrzej Skorupski,,
- The Institute of Computer Science
Publication size in sheets0.5
Book Napieralski Andrzej (eds.): Proceedings of 23rd International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2016, vol. CFP16MIX-CDR, 2016, Lodz University of Technology, Department of Microelectronics and Computer Science, ISBN 978-83-63578-08-4, 538 p.
Keywords in Englishencryption, reversible logic circuits, reconfigurable reversible gate, FPGA
projectDevelopment of new algorithms in the areas of software and computer architecture, artificial intelligence and information systems and computer graphics . Project leader: Rybiński Henryk, , Phone: +48 22 234 7731, start date 18-05-2015, end date 30-11-2016, II/2015/DS/1, Completed
WEiTI Działalność statutowa
Languageen angielski
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Score (nominal)15
ScoreMinisterial score = 15.0, 27-03-2017, BookChapterMatConfByIndicator
Ministerial score (2013-2016) = 15.0, 27-03-2017, BookChapterMatConfByIndicator
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