High Resolution Intelligent Cyclic A/D Converters with Low Resolution Internal Feedback D/A Converters

Konrad Jędrzejewski , Jakub Paweł Jasnos


Intelligent cyclic A/D converters (IC ADCs), considered in the paper, employ an original A/D conversion method and the corresponding architecture based on application of the analytical approach to optimization of adaptive estimation algorithms [1]. The approach permits to determine analytically the most efficient values of converter parameters which guarantee maximal performance of conversion under given permissible probability of saturation. General principles of design and operation of IC ADCs were presented and discussed in [2-3]. The first prototype of IC ADC was designed in Institute of Electronic Systems, Warsaw University of Technology and realized in CMOS technology [4]. Experience acquired during the design process and measurements of the prototype and its components inclined to start the investigation on modification of the IC ADC architecture, in particular in order to simplify the complexity of the internal feedback D/A sub-converter as well as to decrease gains of internal amplifiers in subsequent cycles of conversion. In this paper, a new concept of solution of these problems is presented. Intelligent cyclic ADCs belong to the class of recursive (recirculating) sub-ranging [5] (known also as cyclic, multi-pass) A/D converters whose classical examples are described in [6-9]. Cyclic A/D converters provide the reasonable resolution, speed of conversion, size and power consumption characteristics of converters. In the conventional cyclic A/D converters, the way of forming the output codes of converted samples consists in cyclical shifting of sub-codes (“observations") taken from the output of the analog (rough) internal A/D sub-converter and appropriate “gluing" them to the end of the output code obtained in the previous cycle. In the conventional cyclic ADCs, to avoid errors related to the possible saturation in internal A/D subconverters, the dedicated techniques consisted in introduction of additional [...]
Author Konrad Jędrzejewski (FEIT / PE)
Konrad Jędrzejewski,,
- The Institute of Electronic Systems
, Jakub Paweł Jasnos
Jakub Paweł Jasnos,,
Journal seriesElektronika - konstrukcje, technologie, zastosowania, ISSN 0033-2089, []
Issue year2013
Publication size in sheets0.5
URL http://www.sigma-not.pl/wyszukaj-0-0-10-42910428-high-resolution-intelligent-cyclic-a-d-converters-with-low-resolution-internal-feedback-d-a-converters7.html
Languageen angielski
Score (nominal)8
ScoreMinisterial score = 5.0, 04-09-2019, ArticleFromJournal
Ministerial score (2013-2016) = 8.0, 04-09-2019, ArticleFromJournal
Citation count*1 (2020-09-03)
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