Oversampling ΣΔ Analog-to-Digital Converters Modeling Based on VHDL

R Baraniecki , Przemysław Dabrowski , Konrad Hejn


The paper presents a VHDL model of an oversampling ΣΔ analog-to-digital converter created on the behavioral hierarchy level. Although VHDL has been primarily devoted to digital circuit design, it can also be applied to certain mixed-signal circuits. The model of the analog part is as simple as possible and includes only necessary parameters that enable to determine the potential resolution of a converter. The model of the digital part is described in the synthesizable subset of VHDL and parameterized according to the word length and the type of arithmetic applied. The validation process of the converter model is also shown. It is performed by a VHDL simulator and a postprocessor tool enabling to carry out FFT. Simulation results enclosed prove the efficiency of the design approach presented.
Author R Baraniecki
R Baraniecki,,
, Przemysław Dabrowski
Przemysław Dabrowski,,
, Konrad Hejn ISE
Konrad Hejn,,
- The Institute of Electronic Systems
Journal seriesAnalog Integrated Circuits and Signal Processing, ISSN 0925-1030, 1573-1979
Issue year1998
Keywords in Englishbehavioral modeling and simulation, Circuits and Systems, decimator, Electronic and Computer Engineering, RTL synthesis, Sigma-delta modulator, Signal, Image and Speech Processing, VHDL
URL http://link.springer.com/article/10.1023/A%3A1008211605358
Score (nominal)0
Citation count*0 (2015-04-22)
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