Improved yield model for submicron domain

Witold Pleskacz , Wojciech Maly

Abstract

This paper describes a new manufacturing yield model for submicron VLSI circuits. This model attempts to handle process induced differences between IC layout and actual IC topography. The presented model focuses on the random nature of over and under etching phenomenon. The relevance of the new yield model in submicron domain is analyzed. Examples of yield calculations using the proposed model are presented as well
Author Witold Pleskacz (FEIT / MO) - [Department of Electrical and Computer Engineering (ECE) [Carnegie Mellon University (CMU)]]
Witold Pleskacz,,
- The Institute of Microelectronics and Optoelectronics
- Department of Electrical and Computer Engineering
, Wojciech Maly
Wojciech Maly,,
-
Pages2-10
Publication size in sheets0.5
Book Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - DFT 1997, 1997, IEEE, ISBN 0818681683, 314 p.
Keywords in EnglishComputer aided manufacturing, Conducting materials, etching, IC layout, IC topography, integrated circuit layout, Integrated circuit modeling, integrated circuit yield, manufacturing yield model, Modems, over etching phenomenon, process induced differences, Pulp manufacturing, semiconductor process modelling, submicron domain, surfaces, under etching phenomenon, Very large scale integration, Virtual manufacturing, VLSI
DOIDOI:10.1109/DFTVS.1997.628303
URL https://ieeexplore.ieee.org/document/628303/
Languageen angielski
Score (nominal)0
Publication indicators WoS Citations = 5; GS Citations = 8.0
Citation count*8 (2020-09-15)
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* presented citation count is obtained through Internet information analysis and it is close to the number calculated by the Publish or Perish system.
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