An efficient approach to the measurement and characterization of MOSFET capacitances
Marcin Sadowski , D Tomaszewski
AbstractThis article describes an improved methodology of estimation of the components of MOS transistor gate capacitances. It uses transistors on a test structure, which was designed for the purpose of a general characterization of CMOS technology and devices. The presented method is based on a comparison of the appropriate C–V characteristics of transistors of different gate dimensions. This allows efficient elimination of undesired parasitic capacitances of the measurement setup.
|Journal series||Microelectronics Reliability, ISSN 0026-2714|
|Publication indicators||: 2006 = 0.815 (2) - 2007=0.922 (5)|
|Citation count*||2 (2013-01-30)|
* presented citation count is obtained through Internet information analysis and it is close to the number calculated by the Publish or Perish system.