An efficient approach to the measurement and characterization of MOSFET capacitances

Marcin Sadowski , D Tomaszewski

Abstract

This article describes an improved methodology of estimation of the components of MOS transistor gate capacitances. It uses transistors on a test structure, which was designed for the purpose of a general characterization of CMOS technology and devices. The presented method is based on a comparison of the appropriate C–V characteristics of transistors of different gate dimensions. This allows efficient elimination of undesired parasitic capacitances of the measurement setup.
Author Marcin Sadowski (FEIT / MO)
Marcin Sadowski,,
- The Institute of Microelectronics and Optoelectronics
, D Tomaszewski
D Tomaszewski,,
-
Journal seriesMicroelectronics Reliability, ISSN 0026-2714
Issue year2000
Vol40
No6
Pages1045-1049
DOIDOI:10.1016/S0026-2714(99)00254-1
URL http://www.sciencedirect.com/science/article/pii/S0026271499002541
Score (nominal)20
Publication indicators WoS Impact Factor: 2006 = 0.815 (2) - 2007=0.922 (5)
Citation count*2 (2013-01-30)
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