Improving fault coverage in system tests
AbstractThe paper is devoted to the problem of self-testing in system environment (field diagnosis and maintenance at the end user). It discusses test process decomposition in the context of increasing hardware complexity and proliferation of embedded DFT and BIST circuitry in the commercial off-the shelf VLSI chips (COTS). Test observability is improved with the use of various on-line monitoring mechanisms. To optimize test effectiveness we use special tools based on direct and indirect fault coverage analysis
|Book||On-Line Testing Workshop, 2000. Proceedings. 6th IEEE International, 2000|
|Keywords in English||BIST, built-in self test, COTS, design for testability, DFT, direct fault coverage analysis, fault diagnosis, field diagnosis, hardware complexity, indirect fault coverage analysis, integrated circuit testing, observability, off-the shelf VLSI chips, on-line monitoring mechanisms, self-testing, system testing, system tests, test effectiveness, test observability, test process decomposition, VLSI|
|Publication indicators||= 1; = 0; = 1.0|
|Citation count*||1 (2020-09-20)|
* presented citation count is obtained through Internet information analysis and it is close to the number calculated by the Publish or Perish system.