Improving fault coverage in system tests

Janusz Sosnowski


The paper is devoted to the problem of self-testing in system environment (field diagnosis and maintenance at the end user). It discusses test process decomposition in the context of increasing hardware complexity and proliferation of embedded DFT and BIST circuitry in the commercial off-the shelf VLSI chips (COTS). Test observability is improved with the use of various on-line monitoring mechanisms. To optimize test effectiveness we use special tools based on direct and indirect fault coverage analysis
Author Janusz Sosnowski (FEIT / IN)
Janusz Sosnowski,,
- The Institute of Computer Science
Book On-Line Testing Workshop, 2000. Proceedings. 6th IEEE International, 2000
Keywords in EnglishBIST, built-in self test, COTS, design for testability, DFT, direct fault coverage analysis, fault diagnosis, field diagnosis, hardware complexity, indirect fault coverage analysis, integrated circuit testing, observability, off-the shelf VLSI chips, on-line monitoring mechanisms, self-testing, system testing, system tests, test effectiveness, test observability, test process decomposition, VLSI
Languageen angielski
Score (nominal)0
Publication indicators Scopus Citations = 1; WoS Citations = 0; GS Citations = 1.0
Citation count*1 (2020-09-20)
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