Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPGAs

Andrzej Kraśniewski

Abstract

We present an extension of a procedure for self-testing of an FPGA that implements a user-defined function. This extension, intended to improve the detectability of FPGA delay faults, exploits the reconfigurability of FPGAs and is based on modifying the functions of LUTs in the section under test. A modification procedure replaces a user-defined function of each LUT with a specific function that preserves the blocking capability and input-output transition pattern of the original function. We show that the proposed method significantly increases the susceptibility of FPGA delay faults to random testing.
Author Andrzej Kraśniewski (FEIT / IT)
Andrzej Kraśniewski,,
- The Institute of Telecommunications
Pages675-684
Publication size in sheets0.5
Book Hartenstein Reiner W., Grünbacher Herbert (eds.): Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing, Lecture Notes In Computer Science, no. 1896, 2000, Springer Berlin Heidelberg, ISBN 978-3-540-67899-1, [978-3-540-44614-9], 858 p., DOI:10.1007/3-540-44614-1
Keywords in Englishlogic design
DOIDOI:10.1007/3-540-44614-1_72
URL http://link.springer.com/chapter/10.1007/3-540-44614-1_72
Languageen angielski
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2000 Krasniewski Exploiting Reconfigurability.pdf 152.93 KB
Score (nominal)10
Score sourcejournalList
Publication indicators GS Citations = 19.0
Citation count*19 (2015-04-26)
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