Self-testing of FPGA delay faults in the system environment

Andrzej Kraśniewski

Abstract

We propose a procedure for self-testing of an FPGA programmed to implement a user-defined function. The procedure is intended to improve the detectability of FPGA delay faults. This improvement is obtained by modifying the functions of LUTs in the section under test, so that each LUT implements a XOR function. We show that, despite many potential problems, the proposed modification can significantly enhance the susceptibility of FPGA delay faults to random testing
Author Andrzej Kraśniewski (FEIT / IT)
Andrzej Kraśniewski,,
- The Institute of Telecommunications
Pages40-41
Book (eds.): Proceedings of the 6th IEEE International On-Line Testing Workshop, 2000, IEEE Computer Society, ISBN 0-7695-0646-1, 220 p.
Keywords in Englishautomatic testing, built-in self-test, Delay, delays, fault location, field programmable gate arrays, FPGA delay faults, FPGA testing, integrated circuit testing, logic testing, LUT-based FPGAs, random testing, self-testing, system environment, table lookup, Test pattern generators, user-defined function, XOR function
DOIDOI:10.1109/OLT.2000.856610
Languageen angielski
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2000 Krasniewski Self-Testing of FPGA Delay.pdf 187.79 KB
Score (nominal)0
Publication indicators GS Citations = 6.0
Citation count*6 (2015-04-26)
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* presented citation count is obtained through Internet information analysis and it is close to the number calculated by the Publish or Perish system.
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