A high-performance VLSI architecture of 2D DWT processor for JPEG2000 encoder

Michał Staworko , Damian Modrzyk


In this paper we present a hardware architecture of the lifting-based, two-dimensional discrete wavelet transform. The proposed architecture implements both lossless (5/3) and lossy (9/7), multi-level DWT with an embedded, symmetric extension at tile boundaries. The wavelet processor is an integral part of the hardware JPEG2000 encoder oriented for HD video applications. This article discusses optimization methods, introduced to increase design throughput up to 800 MSamples/s and solutions that rationalize the circuit area. The results of synthesis for FPGA and ASIC technology are presented.
Author Michał Staworko (FEIT / IT)
Michał Staworko,,
- The Institute of Telecommunications
, Damian Modrzyk
Damian Modrzyk,,
Book Proceedings of the 2011 IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2011, IEEE Computer Society, ISBN 978-1-4244-9753-9, 1-350 p., DOI:10.1109/DDECS.2011.5783025
DDECS 2011 spis tresci.pdf / No licence information (file archived - login or check accessibility on faculty)
Keywords in EnglishJPEG2000, discrete wavelet transform, VLSI, 2D DWT processor, application specific integrated circuits, ASIC technology, data compression, discrete wavelet transforms, electronic engineering computing, field programmable gate arrays, FPGA technology, hardware JPEG2000 encoder, HD video applications, high-performance VLSI architecture, multilevel DWT, optimisation, optimization methods, symmetric extension, tile boundary, two-dimensional discrete wavelet transform, video coding, VLSI
URL http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6015938&contentType=Conference+Publications&sortType%3Dasc_p_Sequence%26filter%3DAND%28p_IS_Number%3A6015915%29%26pageNumber%3D2
Languageen angielski
06015938.pdf 400.78 KB
Score (nominal)10
Citation count*2 (2016-01-27)
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