On the influence of arithmetic underflow rounding standard on the speed of FDTD modeling
- Maciej Sypniewski,
- W.K. Gwarek
This paper presents the influence of arithmetic underflow rounding operations on the speed of FDTD analysis. It is shown that the underflow treatment according to the IEEE standard 754 (commonly accepted and implemented in modern arithmetic processors) may sometimes result in drastic slowdown of the speed of computing. The effect is much more pronounced in some of the most modern and most used processors. The ways to circumvent the effect by specific software operations are discussed.
- Record ID
- 1795-1798 Vol.3
- Microwave Symposium Digest, 2004 IEEE MTT-S International, vol. 3, 2004
- Keywords in English
- arithmetic processors, arithmetic underflow rounding standard, circuit simulation, circuit testing, computational electromagnetics, computational modeling, computing speed, FDTD modeling, finite difference methods, finite difference time-domain analysis, floating point arithmetic, Floating-point arithmetic, IEEE standard 754, IEEE standards, microwave antennas, microwave circuits, Microwave theory and techniques, Modems, software operations, Time domain analysis, underflow treatment
- DOI:10.1109/MWSYM.2004.1338949 Opening in a new tab
- Score (nominal)
- Uniform Resource Identifier
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