New trends in logic synthesis for both digital designing and data processing
FPGA devices are equipped with memory-based structures. These memories act as very large logic cells where the number of
inputs equals the number of address lines. At the same time, there is a huge demand in the market of Internet of Things for
devices implementing virtual routers, intrusion detection systems, etc.; where such memories are crucial for realizing pattern
matching circuits, IP address tables, and other. Unfortunately, existing CAD tools are not well suited to utilize capabilities
that such large memory blocks offer due to the lack of appropriate synthesis procedures. This paper presents methods which
are useful for memory-based implementations: minimization of the number of input variables and functional decomposition.