High Resolution Latched Comparator Implemented in 22 nm FD-SOI Process
AbstractThis paper presents the design of comparator dedicated for high linearity flash ADC, implemented in 22 nm FD-SOI process with 0.8 V supply. The block employs latched dynamic comparator preceded by two-stage preamplifier. The main obstacle to obtain high resolution comparator is transistors' mismatch resulting in relatively high offset voltage of the amplifier. Thus, compensation technique based on trimming of transistor's threshold voltage by means of modulating of back-gate polarization has been employed. The obtained comparator presents resolution of ±3 mV.
|Book||Napieralski Andrzej (eds.): Proceedings of 25th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2018, vol. CFP18MIX-CDR, 2018, Politechnika Łódzka, ISBN 978-83-63578-13-8, 475 p.|
|Keywords in English||Transistors;Threshold voltage;Linearity;Signal resolution;Integrated circuits;Latches;Inverters;Comparator;flash ADC;FD-SOI;back-gate polarization;mismatch compensation|
|Project||THIN but Great Silicon 2 Design Objects. Project leader: Kuźmicz Wiesław,
, Phone: (+48) 22 234 7146, application date 12-09-2013, start date 01-01-2014, planned end date 31-12-2017, end date 30-06-2018, IMiO/2014/ENIAC/1, Completed
THIN but Great Silicon 2 Design Objects. Project leader: Kuźmicz Wiesław, , Phone: (+48) 22 234 7146, application date 12-09-2013, start date 01-01-2014, planned end date 31-12-2017, end date 30-06-2018, IMiO/2014/ENIAC/1, Completed
|Score|| = 15.0, BookChapterMatConfByIndicator|
= 15.0, BookChapterMatConfByIndicator
|Publication indicators||= 1; = 1.0; = 0|
|Citation count*||1 (2020-01-19)|
* presented citation count is obtained through Internet information analysis and it is close to the number calculated by the Publish or Perish system.