Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration

Wojciech Maly , Andrzej Pfitzner , Dominik Krzysztof Kasprowicz , Wiesław Kuźmicz , N. Singh , Z. Chen , N. Shen , X. Li , Yi-Wei Lin , Małgorzata Marek-Sadowska

Abstract

n/a
Author Wojciech Maly
Wojciech Maly,,
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, Andrzej Pfitzner IMiO
Andrzej Pfitzner,,
- The Institute of Microelectronics and Optoelectronics
, Dominik Krzysztof Kasprowicz IMiO
Dominik Krzysztof Kasprowicz,,
- The Institute of Microelectronics and Optoelectronics
, Wiesław Kuźmicz IMiO
Wiesław Kuźmicz,,
- The Institute of Microelectronics and Optoelectronics
, N. Singh
N. Singh,,
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, Z. Chen
Z. Chen,,
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, N. Shen
N. Shen,,
-
, X. Li
X. Li,,
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, Yi-Wei Lin
Yi-Wei Lin,,
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, Małgorzata Marek-Sadowska
Małgorzata Marek-Sadowska,,
-
Pages145-150
Book Napieralski Andrzej: MIXDES 2011 18th International Conference Mixed Design of Integrated Circuits and Systems, 2011, Technical University of Lodz, ISBN 978-83-932075-0-3, 701 p.
Keywords in Englishtwin gate, junctionless, 3D transistor, layout regularity, VeSFET, FinFET, trigate, SOI
Languageen angielski
Score (nominal)10
Citation count*55 (2018-01-31)
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