A Tool for Trading-Off On-Line Error Detection Efficiency with Implementation Cost for Sequential Logic Implemented in FPGAs

Grzegorz Borowik , Andrzej Kraśniewski

Abstract

n/a
Author Grzegorz Borowik (FEIT / IT)
Grzegorz Borowik,,
- The Institute of Telecommunications
, Andrzej Kraśniewski (FEIT / IT)
Andrzej Kraśniewski,,
- The Institute of Telecommunications
Pages488-490
Book Selvaraj Henry, Zydek Dawid (eds.): Proceedings of 21st International Conference on Systems Engineering, 2011, IEEE Computer Society, ISBN 978-0-7695-4495-3, 490 p.
Keywords in Englishdependability, sequential circuit, FPGA, embedded memory block, concurent error detection, trancient fault
DOIDOI:10.1109/ICSEng.2011.100
Languageen angielski
Score (nominal)10
Publication indicators GS Citations = 1.0
Citation count*1 (2018-12-16)
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